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DS2465 - 2.3
SP973T8
30MHz 8-BIT FLASH ADC (TTL/CMOS OUTPUTS)
The SP973T8 is a wideband, full flash analog-to-digital converter that requires no preceding sample and hold. The device contains a full 8-bit D-type latch which ensures that the 8 TTL/CMOS outputs are accurately registered and have a good data valid time at high clock speeds. Operating from a single +5 volt supply the device is capable of conversion rates well in excess of 30MHz and its wideband input allows signals with frequencies up to the Nyquist limit to be digitised with high accuracy. An internal bandgap voltage regulator gives low DC drift over a wide operating temperature range. The SP973T8 is designed for applications where power consumption and package size is at a premium.
D3 D2 D1 D0 (LSB) CLK CLK OR BIAS VRB AVCC AGND 9 10 SP973T8 1 18 D4 D5 D6 D7 (MSB) DGND DVCC VRT VIN VRM
DP18
Fig.1 Pin connections - top view
FEATURES
I I I I I I I I
Flash Converter, No Sample and Hold Required Wideband Analog Input 70MHz, 3dB (Typ.) Low Power Consumption (600mW Typ.) Latched TTL/CMOS Compatible Outputs No Missing Codes - Guaranteed Designed for Wideband Operation Single 5V Supply Production Tested at 30MHz
SP973T8 C DP (Commercial - Plastic DIL package)
APPLICATIONS
I I I I I I
Studio Quality Video DBS Broadcast Video High Resolution TV Nucleonics Radar Computing Supply voltage, VCC Output Current Input Voltage, VIN Operating Temperature Storage Temperature 7V 10mA VCC 0C to +70C -65C to +150C
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
CLK CLK OR BIAS VRT
5 6 12 R
+ 13 LSB 4 3 R TTL OUTPUT STAGE 2 1 DVCC D0
VRM VIN AVCC AGND
10 11 R
LATCH
256
ENCODER
8
D LATCH
8
18 17 16
TTL/CMOS OUTPUTS
8 9
MSB 15 14
D7 DGND
R VRB 7
R x 256
Fig.2 Internal block diagram
SP973T8
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions (unless otherwise stated): Tamb = 25C, VCC = +5V 0.25V Full temperature range = 0C to +70C Value Min. 100 110 475 520 1.8 150 Typ. Max. 140 130 735 680 VCC-0.7 1100
DC CHARACTERISTICS Characteristic Power Supply Supply current Power dissipation Analog Input Input range Input bias current 3dB bandwidth Input capacitance Reference Ladder Ladder resistance Ladder voltage (top) Ladder voltage (bottom) Ladder offset (top) Ladder offset (bottom) Ladder temp. coeff. Clock Input Logic '1' voltage Logic '1' current Logic '0' voltage Logic '0' current Digital Outputs Logic '1' voltage Logic '0' voltage Static performance Differential non-linearity Integral non-linearity Symbol Temp. Test level Units Conditions
ICC PD VIN IIN f3db CIN RD VRT VRB VRT0 VRB0 RTC VIH IIH VIL IIL VOH VOL DNL INL
Full 25 Full 25 Full 25 25 25 25 Full Full 25 25 Full Full 25 Full 25 Full 25 Full 25 Full 25 Full 25
4 1 4 1 4 1 4 4 1 4 4 5 5 5 4 1 4 1 4 1 4 1 4 4 4 4
120 600 390 70 30 440 4.3 2.3 -4 +3 1.5 4.3 3.3
mA mA mW mW V A MHz pF V V mV mV /C V A V A V V V V LSB LSB LSB LSB A swing of 1V centred on the voltage applied to the CLK pin VIN = VRT
325 1.8
550 VCC-0.7
2.75 1.75 3.3 3.5
VCC 25 VCC-1.0 2
3.8 0.1
0.4 0.4 1 0.5 1 1
Into Standard LS TTL Load
AC CHARACTERISTICS (Refer to Fig.7) Characteristic Clock min. high Clock min. low Max. conversion rate Aperture delay Output data delay Output rise time output fall time Dynamic Performance Differential non-linearity Integral non-linearity S/N ratio Effective No. of bits Bit Error Rate Symbol Temp. Test level tPW1 tPW0 tAD tD tR tF DNL INL SNR ENOB BER 25 25 Full 25 25 25 25 25 25 25 25 25 4 4 4 5 4 4 4 1 1 1 4 4 1 4 4 4 Value Min. 10 10 30 Typ. Max. Units ns ns MHz ns ns ns ns +1 2 LSB LSB dBc dBc dBc bits bits bits Conditions
50 3 7 6 8 0.5 1 44.5 44.1 43.3 7.1 7.0 6.9 1 in 109
AIN = 15MHz at FS
-0.85 40.9 6.5
With FCLK = 30MHz AIN MAX = 10MHz at FS AIN MAX = 10MHz at FS AIN MAX = 1MHz at FS AIN MAX = 5MHz at FS AIN MAX = 10MHz at FS AIN MAX = 1MHz at FS AIN MAX = 5MHz at FS AIN MAX = 10MHz at FS
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SP973T8
ELECTRICAL CHARACTERISTICS DEFINITIONS
Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency, as determined by Fast Fourier Transform analysis is 3dB down on the DC level. Aperture Delay The delay between the falling edge of the CLOCK signal and the instant at which the analog input is sampled. Bit Error Rate (BER) The number of spurious code errors produced for any given input sinewave frequency. In this case it is the number of codes occuring outside the histogram cusp for a 3/4 F.S. sinewave. Differential Non-Linearity (DNL) The deviation of any code width from an ideal 1LSB step. Effective Number of Bits (ENOB) This is a measure of the dynamic performance and is calculated from the following expression. ENOB = SNR-1.76 6.02 SNR is the signal-to-noise ratio, in decibels, at the test frequency. Integral Non-Linearity (INL) The deviation of the centre of each code from a reference line which has been determined by a least squares curve fit. Output Data Delay The delay between the 50% point of the falling edge of the clock signal and the 50% point of any data output change. Reference Ladder Offset The voltage error at the ends of the resistor chain caused by the lead frame and bond wire. Signal-to-Noise Ratio (SNR) The ratio of the RMS signal amplitude to the RMS value of 'noise' which is defined as the sum of all other spectral components including harmonics but excluding DC with a full scale analog input signal. Test Levels Level 1 - 100% production tested Level 2 - 100% production tested at 25C and sample tested at specified temperatures Level 3 - Sample tested only Level 4 - Parameter is guaranteed by design and characteristics testing Level 5 - Parameter is a typical value only
PIN DESCRIPTIONS
Pin No. 1, 2, 3, 4 5 6 7 8 9 10 11 12 13 14 15 16, 17, 18 Function D3, D2, D1, D0 CLK CLK VRB AVCC AGND VRM VIN VRT DVCC DGND D7 D6, D5, D4 Description Output data bits 3, 2, 1, 0 Clock input pin Clock threshold level pin Bottom of reference resistor chain 5 Volt power to all circuitry except the TTL output Middle of reference resistor chain Analog input voltage pin Top of reference resistor chain 5 Volt power supply to the TTL output stage Most significant bit (output data bit 7) Output data bits 6, 5, 4
RECOMMENDED OPERATING CONDITIONS
Supply Voltage VCC Reference VRT Reference VRB AVCC to DVCC AGND to DGND Analog Input VIN
+5.0V +4.3V +2.3V 0mV 0mV 2 Vp-p max
THERMAL CHARACTERISTICS
Thermal resistance, chip-to-case jc Thermal resistance, chip-to-ambient jA
DP 20 75
C/W C/W
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SP973T8
APPLICATION NOTES
Analog Input Pin (Fig.3) The analog input of the SP973T8 is connected to 256 comparators which have a combined capacitance of about 30pF. The sample/latch operation of the comparators causes the input capacitance to vary slightly as the comparator input transistors turn on/off. For this reason the input driver circuit should provide a low impedance signal to keep the harmonic distortion levels of the driver to a minimum. The maximum amplitude of the analog input is defined by the setting of the two reference voltages VRT and VRB. Optimum performance will be obtained with the input signal biased midway between VRT and VRB with a peak to peak amplitude of VRT-VRB. The SP973T8 has excellent overload tracking of input signals with amplitudes greater than VRT-VRB, and will not be damaged if the absolute maximum ratings are adhered to.
AVCC +5V REF CHAIN
5V
18k
4.3V
ADC PIN 12
CLAMP LEVEL FOR VIDEO APPLICATIONS 1.5k
ADC INTERNAL RESISTOR CHAIN
2.45V ZN458 PRECISION REFERENCE
ADC PIN 7
VRT
1.5
ANALOG INPUT
Fig.4 Simple reference voltage generation
200A
TTL/CMOS Outputs (Fig.5) The data output levels of the SP973T8 are TTL/CMOS compatible and switch from 0V to +4V. The output circuit is capable of operation at clock frequencies in excess of 60MHz when driving into a standard LSTTL load.
VRB
Fig.3 One of 255 analog inputs connected to pin 11
+5V DVCC
Voltage Reference Pins (Fig.4) The SP973T8 converts analog signals in the range VRB50
DATA OUTPUT
DGND
Fig,5 TTL output stage
4
SP973T8
Clock Input (Fig.6) The SP973T8 will operate at clock frequencies up to and above 30MHz. The clock input has been designed to accept a 1Vpp signal, in either differential or single-ended mode, between the VIH(MAX) and VIL(MIN) levels indicated in the electrical specification. At VIH(MAX) or VIL(MIN) the CLK input will sink 800A or source 3.2mA of current, respectively. (See Fig.6). When used in single-ended operation, CLK may be decoupled to ground so that this input will then self-bias at approximately 1.2V below the supply VCC. It may then be used to bias the CLK input, through a termination resistor, for ACcoupled applications as shown in Fig.8. Alternatively a TTL level clock may be used by inserting an appropriate value resistor in series with the coupling capacitor.
AVCC 450 +5V
450 600 3.8V
CLOCK INPUT
DIFF CLOCK
CLOCK OR BIAS DECOUPLE
800A AGND
800A
Fig.6 Clock input stage
TIMING (Fig.7) The analog input is sampled by the SP973T8 approximately 3ns (tAD) after the falling edge of the clock. Due to the pipeline operation of the device, a further one clock cycle is required to produce the output data. As shown in Fig.7, the output has a good data valid time, enabling the data to be latched at both the rising and falling edges of the clock.
However, for clock frequencies above 25MHz the clock-tooutput delay time may lead to an inadequate data set up time relative to the rising clock edge and it is therefore recommended that the output data is latched on the falling clock edge.
SAMPLE N
SAMPLE N+1
SAMPLE N+2
SAMPLE N+3
VIN tAD tCYC CLOCK tpw0 tD DATA VALID N-1 DATA VALID N DATA VALID N+1 tpw1
DATA OUTPUT
4V DATA VALID N-2 0V
PIPELINE DELAY
Fig.7 Timing diagram
5
SP973T8
Circuit Board Construction (Fig.8) Excellent performance can be obtained from this ADC using only one solid ground plan for both analog and digital signals. With all flash ADCs it is important to restrict digital crosstalk into the input, not only within the wanted signal bandwidth but also at frequencies between Nyquist and clock, as such signals will be aliased down into the wanted signal bandwidth. We can give the designer two useful suggestions to reduce the above. First, due to the on-chip clock regeneration circuit, a low level clock can be fed to the ADC 1V p-p is recommended. The second suggestion is the addition of a small bead inductor in series with and close to the device analog input. Supply line decoupling is very important when dealing with a mix of analog and digital signals as they can provide a source of digital feedback from the digital output currents. It is wise, therefore, to decouple the SP973T8 close to the device supply pins with good quality, high frequency, low inductance capacitors. Due to the high clock rates involved, long clock lines to the device should be avoided to reduce the noise pick up.
D0 (LSB) D1 D2 D3 DATA OUTPUTS (TTL/CMOS COMPATIBLE)
1 2 3
0.1 CLOCK 50 0.1
18 17 S P 9 7 3 T 8 16 15 14 13 12 11 10
10n 10n 10nF
D4 D5 D6 D7 (MSB) DGND DVCC +VE REF VRT ANALOG INPUT MID REF VRM
4 5 6 7 8 9
-VE REF VRB AVCC AGND 10n
10n
NOTE: DECOUPLE CLOSE TO PINS
Fig.8 Test/application circuit
6
SP973T8
7
SP973T8
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES * FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55 * ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 * JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 * NORTH AMERICA Integrated Circuits and Microwave Products Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023. Hybrid Products, Farmingdale, USA Tel (516) 293 8686 Fax: (516) 293 0061. * SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 * SWEDEN Stockholm, Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 * UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide.
(c) GEC Plessey Semiconductors 1994 Publication No. DS2465 Issue No. 2.3 January 1994
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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